1. Field of the Invention
The present invention relates generally to a synchronizer for high speed telecommunications signals. More particularly, the present invention relates to a framer for DS1 telecommunications signals which reduces the amount of memory required for synchronization by utilizing a state machine.
2. State of the Art
The DS1 telecommunications signal is a well established standard in telecommunications in the United States as well as in other parts of the world. The DS1 signal is defined by standards ANSI T1.403-1989; ANSI T1.107-1988; ANSI-T1M1-3/93-005R1 April 1993 as a 1.544 MHz signal carried by a T1 trunk. The frame of the DS1 signal consists of one hundred ninety-three bits (each repeating at a rate of 8 kHz). One hundred ninety-two of the one hundred ninety-three bits are used to transmit twenty-four eight bit DS0 signals, while one other bit is used for DS1 "overhead". The overhead bit is typically used for synchronization purposes as well as for signalling synchronization and a maintenance channel.
Various formats are known in conjunction with DS1 signals, including the "D4 SF" or "superframe" format, the "SLC-96" format, and the "ESF" or "extended superframe" format. The SF and ESF formats are SONET (synchronous optical network) compatible. In the shperframe format, twelve frames of DS1 signals are utilized together to provide twelve overhead bits which are used for frame synchronization and signalling. In particular, every other (i.e., six) of the twelve overhead bits of the twelve frame superframe are used for frame synchronization, while the other six overhead bits are used for signalling synchronization, i.e., locating signalling bit location. The bit pattern of the frame synchronization bits (also called the Ft bits) is an alternating 010101 pattern. The signalling synchronization bits (also called the Fs bits), on the other hand, are provided with a 001110 pattern and are used to identify the sixth and twelfth DS0s of the frame, where one bit of the DS0 can be used for signalling. In the sixth frame, the signalling bit of the DS0 is known as the "A" bit, while in the twelfth frame, the signalling bit is known as the "B" bit. If there is no signalling, the six signalling synchronization bits of the superframe are not utilized. However, if there is signalling, the A and B bits provide either two state or four state signalling. In two state signalling which provides redundancy for error suppression and faster response, each B bit is set equal to an associated A bit (A=B). Thus, two states are present: 00, 11. In four state signalling, A and B are independent, and each can assume either the 0 or 1 values. Thus four states are present: 00, 01, 10, 11.
The SLC-96 format generally includes groupings of seventy-two DS1 frames. The synchronization (Ft) bits in the SLC-96 format utilize the same alternating bit pattern (010101) as used in the D4 SF format. However, the signalling synchroniation Fs bits are utilized differently. In particular, in SLC-96, the Fs bits of the first twenty-four frames and last twenty-four frames of the seventy-two frame superframe utilize the 001110 pattern and are signalling bits to identify the frames in which the A and B bits are located. However, the middle twenty-four Fs bits are used to send a control message. In addition, the A and B bits of the SLC-96 format provide for nine state signalling with the A and B bits being independent and assuming either a pattern of all zeros, all ones, or alternating zeros and ones.
The ESF format utilizes a superframe of twenty-four DS1 frames. Of the twenty-four overhead bits, six bits are used for frame synchronization, six bits are used for error checking (CRC-6), and twelve bits are used for a data channel. The six frame synchronization bits are distributed over the twenty-four frames and assume the pattern 001011.
Regardless of the format utilized, large buffers have been used in the art to synchronize the receiving apparatus to the incoming DS1 frame. As data is received, the DS1 signal is placed in the buffer which is one hundred ninety-three bits wide and at least eight bits deep (e.g., a 193.times.8 dual port RAM). In fact, for the SLC-96 and ESF formats, the buffers of the art have been at least twenty-four bits deep. After the data fills the buffer, each of the one hundred ninety-three columns of data are scanned to determine whether they contain the expected eight-, or twenty-four bit pattern of overhead data, and the column containing the expected overhead format is then identified as the overhead location in the data frame. It should be appreciated that in matching the data in the buffer column to the expected pattern of overhead data, either different phases of the expected pattern must be compared to the data present in each column, or different phases each column must be compared to the expected pattern. Regardless, even after the overhead location of the data frame is found, data is continually sent to the buffer, and pattern of the bits of the expected overhead location is checked to establish that the frame synchronization has been maintained.
While the framing techniques of the prior art establish frame relatively accurately and quickly, they require a large amount of buffer memory. In integrated circuits, large amounts of memory takes up valuable real estate on the silicon chip, and resultingly either limits the other functions available on the chip, or increases the size of the chip, thus increasing the cost of the chip. This is particularly true when synchronization is required in multi-channel applications such as multi-DS1 customer premise equipment (CPE) and SONET.